#
# this makefile fragment is concerned with generation of make files
# and other standard files from templates. It is based on work done by
# Rod Whitby and others at Austek Microsystems in 1991.
#
# $Copyright: (c) 1997-2008 Thomas Dejanovic $ 
#

# Local targets

targets ::
	@echo
	@echo "generation.mak:"
	@echo "--------------"
	@echo
	@echo "  makefile       -- Update the Makefile from the template"
	@echo "  force_makefile -- Recreate the Makefile from the template"
	@echo
	@echo "  SUBMODULE=<submodule_name> submodule -- create new submodule"
	@echo "  SUBMODULE=<submodule_name> clobber_submodule -- delete it"
	@echo
	@echo "  <name>.v_new -- generate a verilog module file called <name>.v from a template."
	@echo



# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Makefile generation targets

# Initialise these variables here - they will be overridden by included
# makefile fragments.


NEW_SUBMODULE               = 
NEW_SOURCE_FILES            = 

MAKEFILE_PREPEND_INCLUDED   = 0
MAKEFILE_POSTPEND_INCLUDED  = 0

XILINX_ISE_INCLUDED         = 0
IVERILOG_INCLUDED           = 0
HATCH_INCLUDED              = 0

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

MAKEFILE_DEPEND_FILES = ${PROJ_TEMPLATES}/makefile_template \
		        ${PROJ_SCRIPTS}/generate \
		        ${PROJ_MAKEFILES}/generation.mak

.PHONY : makefile

makefile :
	${MAKE} MAKEFILE_DEPENDS="${MAKEFILE_DEPEND_FILES}" Makefile

force_makefile :
	touch .$@_timestamp
	${MAKE} MAKEFILE_DEPENDS=.$@_timestamp Makefile
	rm -f .$@_timestamp


# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# generate the makefile

Makefile : ${MAKEFILE_DEPENDS}
	${PROJ_SCRIPTS}/generate --makefile \
	  --MODULE=${MODULE} \
	  --PATH=${MODULE_PATH} \
	  --PREPEND=${MAKEFILE_PREPEND_INCLUDED} \
	  --SOURCE_FILES="${LOCAL_SOURCE_FILES}" \
	  --SOURCE_FILES="${NEW_SOURCE_FILES}" \
	  --SUBMODULES="${SUBMODULES}" \
	  --SUBMODULES="${NEW_SUBMODULE}" \
	  --XILINX_ISE="${XILINX_ISE_INCLUDED}" \
	  --IVERILOG="${IVERILOG_INCLUDED}" \
	  --HATCH="${HATCH_INCLUDED}" \
	  --VERILOG_MODULE_DIRS="${VERILOG_MODULE_DIRS}" \
	  --VERILOG_LIBRARY_DIRS="${VERILOG_LIBRARY_DIRS}" \
	  --VERILOG_LIBRARY_FILES="${VERILOG_LIBRARY_FILES}" \
	  --VERILOG_NETLIST_DIRS="${VERILOG_NETLIST_DIRS}" \
	  --VERILOG_BLACK_BOX_DIRS="${VERILOG_BLACK_BOX_DIRS}" \
	  --POSTPEND=${MAKEFILE_POSTPEND_INCLUDED}

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Targets for local Makefiles

Makefile.prepend Makefile.postpend :
	cp ${PROJ_TEMPLATES}/$@ $@
	chmod oug+rw $@
	svn add $@

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Submodule generation targets

.PHONY : submodule

submodule :
	svn mkdir ${SUBMODULE}
	cd ${SUBMODULE} ; \
	  ${MAKE} -f ${PROJ_MAKEFILES}/generation.mak Makefile \
	    MODULE=${SUBMODULE} \
	    MODULE_PATH=${MODULE_PATH}/${SUBMODULE}; \
	  svn add Makefile
	${MAKE} force_makefile NEW_SUBMODULE=${SUBMODULE}

.PHONY : clobber_submodule

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Rules for generation of module files from templates

%.v_new :
	${PROJ_SCRIPTS}/generate --module_template \
	  --MODULE_NAME=$*.v

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Special hierarchical rules that don't fit the normal pattern

.PHONY : all.makefile sub.makefile

all.makefile :
	${MAKE} makefile
	${MAKE} sub.makefile

sub.makefile :
	${MAKE} TARGET="makefile" pre-traverse

.PHONY : all.force_makefile sub.force_makefile

all.force_makefile :
	${MAKE} force_makefile
	${MAKE} sub.force_makefile

sub.force_makefile :
	${MAKE} TARGET="force_makefile" pre-traverse

#---------------------------------------------------------------------
# Local Variables:
# mode: makefile
# End:
# End of generation.mak
